Chinese translation for "clock generator"

时钟产生器
时钟发生器
时钟脉冲发生器

Related Translations:

clock:  n.1.钟；挂钟，座钟，上下班计时计。2.〔俚语〕记秒表，卡马表；〔美俚〕〔pl.〕驾驶仪表，速度表，里程计。3.〔英俚〕(人的)面孔。4.〔the C-〕【天文学】时钟座〔星座名〕。5.【自动化】(电子计算机的)时钟脉冲(器)。短语和例子a Dutch clock(报时发杜鹃鸣声的)杜鹃钟 (＝cuckoo-clock)。 an eight-day clock八日上一次发

clock number:  上班计时卡号码

clocked fliflop:  时标触发器定时触发器

clock change:  时钟更改

cuckoo clock:  (报时似杜鹃鸣声的)杜鹃钟。

interval clock:  间隔时钟间隔时种

doomsday clock:  末日钟声世界末日之钟世界末日钟

clock washer:  钟用垫圈

clocked up:  拿到

minor clock:  小时钟

Example Sentences:

	1.	Advanced multi - clock mechanism and clock generator 先进的多时钟机制和时钟发生器
	2.	The sampling clock generator must also have adequate spectral purity 时钟发生电路固有的抖动应该足够小。
	3.	High - frequency clock generator based on dds hybrid pll 基于锁相混频原理的高精度激光外差干涉信号的处理方法研究
	4.	But to design and integrate a clock generator into a chip is a far cry from the out - chip one 文中研究的锁相环时钟发生器就针对该要求而设计。
	5.	Simulation results on a spread spectrum clock generator were accorded with the requirements and demonstrate the validity of the models proposed 仿真结果显示，这个系统达到了预期的要求，证明这个模拟器是比较有效的方法。
	6.	As is known to all , the former pcb system uses an out - chip oscillator , which is called out - chip clock generator , to provide system with clocks 比如以前的板极系统多数使用电路板上的外部振荡电路作为系统的时钟发生器。
	7.	The pll clock generator , which has been integrated in " line " , will be taped out through tsmc 0 . 25um mpw ( multi - project wafer ) project 该锁相环时钟发生器采用了tsmc0 . 25umcmos制造工艺，它将和“ line ”芯片一起在tsmc的多晶圆( mpw )项目下流片。
	8.	Ieee j . solid - state circuits , 2003 , 8 : 689 - 695 . 10 alvandpour a et al . a 2 . 5ghz 32mw 150nm multiphase clock generator for high - performance microprocessor 模拟结果显示，在0 . 18m cmos工艺下，这种加法器的延时为485ps ，平均功耗仅为25 . 6mw ，达到了高速低功耗的目标。
	9.	A monolithic clock synthesis pll , which is expected to be a reference 800mhz clock generator in accelerometer system , has been designed and characterized in this paper 本文设计了一种采用锁相环频率合成技术实现的800mhz时钟发生器,用作加速度传感器读出电路的基准时钟信号。
	10.	A fast simulation environment has been developed using matlab and simulink for behavioral level simulation of spread spectrum clock generator based fractional - n frequency synthesizers 摘要提出了一种展频时钟生成的方法，使用matlab和simulink开发出了快速模拟基于分数n型频率合成器的展频时钟生成器的环境。

Similar Words：

"clock gate" Chinese translation, "clock gating" Chinese translation, "clock gauge" Chinese translation, "clock gear" Chinese translation, "clock generation" Chinese translation, "clock generator and driver" Chinese translation, "clock glass" Chinese translation, "clock golf" Chinese translation, "clock hammer" Chinese translation, "clock hand" Chinese translation